High-efficiency photovoltaic back-contact solar cell structures and manufacturing methods using semiconductor wafers

ABSTRACT

A back contact back junction solar cell using semiconductor wafers and methods for manufacturing are provided. The back contact back junction solar cell comprises a semiconductor wafer having a doped base region, a light capturing frontside surface, and a doped backside emitter region. A frontside and backside dielectric layer and passivation layer provide enhance light trapping and internal reflection. Backside base and emitter contacts are connected to metal interconnects forming a metallization pattern of interdigitated fingers and busbars on the backside of the solar cell.

RELATED APPLICATIONS

This application claims the benefit of provisional patent application61/285,140 filed on Dec. 9, 2009, which is hereby incorporated byreference.

FIELD

This disclosure relates in general to the field of photovoltaics andsolar cells, and more particularly to back contact back junction thinsolar cells and methods for manufacturing.

BACKGROUND

Crystalline silicon currently has the largest market share in thephotovoltaic (PV) industry, accounting for over 80% of the overall PVmarket share. Although going to thinner crystalline silicon solar cellsis long understood to be one of the most potent knobs for PV costreduction (because of the relatively high material cost of crystallinesilicon wafers used in solar cells as a fraction of the total PV modulecost), it is fraught with the problem of mechanical breakage due to thethin and large wafer sizes and to some extent that of light trapping ina thin structure. The requirement of high mechanical yield and reducedwafer breakage rate is further problematic with the realization that forcost-effectiveness, the yields in PV manufacturing factories must bevery high. On a standalone crystalline silicon solar cell (withoutsupport), going even somewhat below the current thickness range of 140μm-250 μm, starts to severely compromise mechanical yield duringmanufacturing. Thus, any solution to process very thin solar cellstructures either should be fully or partially supported by a hostcarrier throughout the cell process or should be a novelself-supporting, standalone substrate with an accompanying structuralinnovation providing rigidity. High efficiency solar cells areclassically manufactured using expensive patterning techniques such aslithography. The techniques described herein allow for substantial costreduction both because of much less silicon and process simplification,while enabling a high performance high efficiency cell design.

Achieving high cell and module efficiency with low fabrication costs hasalways been an important task for solar cell development andmanufacturing. Back junction/back contacted cell architecture is capableof very high efficiency primarily because there is no metal shading onthe front side, no emitter on the front and the resulting high blueresponse, as well as due to potentially low metal resistance on thebackside. Although, the aforementioned thin substrates and the carrierapproach can, in general, be used with any cell architecture, it isspecifically, conducive to the back junction/back contacted cell. It isknown to those versed in the field that back junction/back contactedcell demands a very high diffusion length to substrate thickness ratio,typically ≧5. In conventional cells, because thickness cannot be reducedeasily the emphasis is to get very high lifetime material—which resultsin a larger minority carrier diffusion length, but increases the wafercost. With thin cells, the diffusion length does not have to be as highresulting in an ease in the material quality requirements, in additionto much less volume of silicon.

SUMMARY

In accordance with the disclosed subject matter, innovative structuresand methods for manufacturing back contact/back junction solar cells areprovided.

In one embodiment, a back contact back junction solar cell usingsemiconductor wafers and methods for manufacturing is provided. The backcontact back junction solar cell comprising a semiconductor wafer havinga doped base region, a light capturing frontside surface, and a dopedbackside emitter region. A frontside and backside dielectric layer andpassivation layer provide enhance light trapping and internalreflection. Backside base and emitter contacts are connected to metalinterconnects forming a metallization pattern of interdigitated fingersand busbars on the backside of the solar cell.

The disclosed subject matter, as well as additional novel features, willbe apparent from the description provided herein. The intent of thissummary is not to be a comprehensive description of the claimed subjectmatter, but rather to provide a short overview of some of the subjectmatter's functionality. Other systems, methods, features and advantageshere provided will become apparent to one with skill in the art uponexamination of the following FIGURES and detailed description. It isintended that all such additional systems, methods, features andadvantages included within this description, be within the scope of theaccompanying claims.

BRIEF DESCRIPTIONS OF THE DRAWINGS

For a more complete understanding of the disclosed subject matter andadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying drawings in which likereference numbers indicate like features and wherein:

FIG. 1 is a cross-sectional diagram of a back contact solar cell that ismade of a bulk silicon wafer;

FIG. 2 is a block diagram of a fabrication process flow for making asolar cell;

FIGS. 3( a-i) are cross-sectional schematic views of a solar cellfabricated according to FIG. 2 after key process steps;

FIGS. 4( a-b) illustrate backside views of two types of backsidereinforcement plates with through plate openings or grid-shaped ribstructures;

FIGS. 5( a-b) illustrate two exemplary metal busbar designs;

FIG. 6 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 7 is a block diagram of a fabrication process flow for making thesolar cell of FIG. 6;

FIG. 8 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 9 is a block diagram of fabrication process flow of making thesolar cell of FIG. 8;

FIG. 10 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 11 is a block diagram of the fabrication process flow for makingthe solar cell of FIG. 10;

FIG. 12 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 13 is a block diagram of the fabrication process flow for makingthe solar cell of FIG. 12;

FIGS. 14( a-k) are cross-sectional schematic views of the fabrication ofthe solar cell of FIG. 12 after key fabrication process steps;

FIG. 15 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 16 is a block diagram of fabrication process flow of making thesolar cell of FIG. 15;

FIG. 17 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 18 is a block diagram of fabrication process flow of making thesolar cell of FIG. 17;

FIG. 19 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 20 is a block diagram of fabrication process flow of making thesolar cell of FIG. 19;

FIG. 21 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer;

FIG. 22 is a block diagram of the fabrication process flow for makingthe solar cell of FIG. 21; and

FIGS. 23( a-k) are cross-sectional schematic views of the fabrication ofthe solar cell of FIG. 21 after key fabrication process steps

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS

The following description is not to be taken in a limiting sense, but ismade for the purpose of describing the general principles of the presentdisclosure. The scope of the present disclosure should be determinedwith reference to the claims. Exemplary embodiments of the presentdisclosure are illustrated in the drawings, like numbers being used torefer to like and corresponding parts of the various drawings.

The following disclosure describes various back contacted cells (BLACcell) on thin wafers made from bulk ingots. Specifically, the wafers maybe made using wire saw or proton implantation and separation. Andalthough, NBLAC cells are used for explanatory purposes (NBLAC definedby N-type base doping), the scope of the disclosed structures andmethods are not intended to be limited to NBLAC cells as one skilled inthe art could apply the disclosed subject matter PBLAC cells (PBLACdefined by p-type base doping, such as boron-based). There are twosub-sections in this disclosure: 1) In the first subsection, the processflows involve growth of the emitter using epitaxial deposition on thewafer as opposed to the entire substrate being grown using epitaxy. 2)In the second section, the emitter is formed on the surface region ofthe wafer using gas phase diffusion in a furnace or using atmosphericpressure chemical vapor deposition (APCVD). For NBLAC cells (havingn-type base) the emitter is p-type, typically boron based, and is formedby boron doping in a furnace or the deposition of APCVD BSG on the wafersurface followed by annealing.

FIG. 1 is a cross-sectional diagram of a back contact solar cell that ismade of a bulk silicon wafer. This solar cell embodiment is referred toas a Flow-1.1 cell. The back contact solar cell has lightly dopedepitaxial emitter everywhere except under contacts (where it is dopedheavily to form the selective emitter contacts), two-sided thermal oxideand LPCVD silicon nitride thin layers, laser ablated contact openings,inkjet printed dopants, electroless-plated metallization, and substratereinforcement. The oxide layer provides passivation to both front andback surfaces while LPCVD silicon nitride acts as an anti-reflectioncoating for the front surface and as wet etch stop for processing on theback surface of the wafer. The substrate reinforcement plate is shown,as an example, attached with alignment to the backside of the cell. Thebackside reinforcement plate may be a continuous plate with throughholes for accessing the emitter and base metal contacts on the backsideof the solar cell. Alternatively, the backside reinforcement plate mayhave one or more larger openings that resemble a grid-shaped structurefor lighter and easier substrate backside access at solar cell modulelevel.

The starting silicon wafer may be either a CZ or FZ wafer. The thinsilicon substrate may be formed by sawing a silicon ingot followed by anoptional surface grinding and polishing, or by cleaving/releasing from athick silicon wafer. The wafer is preferably thin enough for a givenaverage minority carrier lifetime in order to obtain the diffusionlength to wafer thickness ratio of ≧5. On the other hand, the wafershould be robust for surviving the handling and processing conditions.The thickness of the silicon wafer is preferably in the range of 50 μmto 250 μm. The shape of the silicon substrate may be square orpseudo-square with rounded corners. The edges of the thin wafer arepreferable polished to eliminate the micro cracks at the edges in orderto prevent the cracking of the wafer during subsequent processing steps.

FIG. 2 is a block diagram of a fabrication process flow for making theFlow-1.1 solar cell. FIGS. 3( a-i) are cross-sectional schematic viewsof the Flow-1.1 solar cell after key fabrication process steps. As shownin FIG. 2, the solar cell fabrication process starts with texturing. Thefront side surface of the solar cells is textured for reduction of thereflective optical losses. The surface texture is formed by etching in adiluted alkaline solution, such as KOH solution. In the lowconcentration of KOH etching, different crystal planes in silicon areetched at different rates. As a result, randomly distributed pyramidswith various sizes are formed. The texture etching process may beconducted in a single side etching apparatus, in which only the frontside of the silicon substrate is making contact with the etchingsolution or alternatively, both sides of the silicon substrate may betextured by submerging the substrates in the etching solution in a batchetching process. In yet another alternative texturing approach, thetextures may be formed by laser surface ablation. As a laser beam withproper wavelength, power, and duty are scanned across the silicon frontsurface, micro surface cavities with random sizes and shapes are formed.After laser ablation, a short diluted KOH etching may be conducted toremove the silicon debris and further enhanced the surface texturing.After the texturing process, the wafer is cleaned using the standard RCAclean which consists of an organic clean (referred to as SC1) and metalcontaminations clean (referred to as SC2 clean). FIG. 3( a) illustratescross-sectional view of the silicon substrate after the front sidetexturing process.

In the next step, as shown in FIG. 3( b), a thin epitaxial siliconemitter layer is grown on top of the backside silicon surface. In thecase of n-type silicon substrate, the epitaxial emitter layer is p-typein-situ doped, such as by boron doping within the epitaxial growthprocess. Compared with the diffusion based doping process, the in-situepitaxial doping may provide doping profiles that can be tailored forthe best possible open circuit voltage (V_(oc))and current density(J_(sc)). For example, the epitaxial doping can be constant orcontinuously varying (or graded) within the layer thickness, or usemulti-step doping with each doping step resulting in different dopingconcentration. This in general, can facilitate a high open circuitvoltage (Voc) of the solar cell, thus a higher efficiency. The epitaxialemitter layer is preferred to have a thickness in the range of 0.5 μm to3 μm.

As shown in FIG. 2, the next step is surface passivation layer andanti-reflection coating (ARC) layer deposition. Since defects of thesilicon crystal structure at the substrate surface are much more commonthan the defects in the bulk, reduction of the carrier recombination atthe surface defects is an important requirement in achievinghigh-efficiencies for crystalline silicon solar cells—and it is evenmore critical for thin and large silicon wafers because of the largersurface to volume ratio. Surface passivation with dielectric layers isan effective method to reduce the carrier recombination rate at surfacesbecause good surface passivation layers provide reduction of the surfacestate density. In FIG. 2, a thermally grown silicon oxide thin layerwith thickness in the range of 3 nm to 100 nm is used for both front andback side surface passivation. FIG. 3( c) illustrates thecross-sectional view of the wafer after the thin thermal oxidation layergrowth showing the thin oxide layer on both sides of the silicon wafer.

On top of the thin thermal oxide layer, a thin LPCVD silicon nitridelayer, with thickness preferably in the range of 60 nm to 100 nm, isdeposited. Alternatively, the oxide/silicon nitride layers on thebackside may be replaced by an aluminum oxide layer of similar thicknessto provide surface passivation of p-type emitter. The LPCVD siliconnitride layers serve at least three purposes: (1) Optically, combinedwith the thin oxide layer, the silicon nitride layer surface as ananti-reflection coating (ARC) layer at front surface as well as anenhanced internal optical reflection layer for better light trapping atfront surface. At the backside surface, the oxide and nitride (oraluminum oxide) layers, with proper thickness, provides an enhancedinternal optical reflection to serve as part of the back mirror effectscombined with the deposited metal layer on the backside surface. (2)Mechanically, the LPCVD silicon nitride layer (or the aluminum oxidelayer at backside) protects the silicon surface and the thin siliconoxide surface from scratches that may be generated during cellprocessing. It also serves as a barrier layer to prevent impurity andmetal diffusions into the silicon surface therefore avoiding or reducingelectrical shunting. (3) Chemically, the silicon nitride and aluminumoxide layer, especially a LPCVD silicon nitride layer, provides a goodchemical resistant layer during subsequent cell processing steps, suchas removal of the doping glass in diluted HF-based etchants after theannealing the dispensed liquid dopants. In the embodiment shown in FIG.2 of the Flow-1.1 solar cell, a thin layer of LPCVD silicon nitride isdeposited on both sides of the substrates on top of the oxide layer.FIG. 3( d) illustrates the cross-sectional view of the substrate afterthe LPCVD silicon nitride deposition.

As shown in FIG. 2, the next step is to create interdigitated rows ofcontact openings in the aforementioned dielectric layer so theunderlying silicon is exposed. In general, the pattern in which thedielectric will be opened is an inter-digitated fingers and bus bar—thebase and the emitter lines are separated and continuous or a string ofnon-overlapping spots. The purpose of the base and emitter contactopenings is for subsequent selective doping. In the NBLAC embodiment,base contact open will be doped heavily with n-type phosphorous materialand emitter contact open will be doped with p-type Boron. Both base andemitter opening regions are opened at the same time in this step. Aspecific implementation of this step may be carried out using a directlaser ablation of the oxide layer. A pulsed picosecond laser in visibleor UV wavelength is conducive to ablating an oxide layer. FIG. 3( e)illustrates the dielectric base and emitter openings in thecross-sectional drawing.

As shown in FIG. 2, the next step is to apply both n and p-type dopantsselectively over the base and the emitter contact open areas followingthe previously defined inter-digitated pattern. The dopants will coverthe openings and can have a slight overlap with the dielectric layer (ontop of it). For the NBLAC specific embodiment, on the emitter area thisdopant has to be p⁺⁺ type (for instance boron based), and on the basecontact area it has to be n⁺⁺ type (phosphorous based). A specificmethod of implementation of the dopants is using the inkjet printingtechnique. In addition, specific examples of the inks that may bedisposed are silicon nano-particle based phosphorous and boron inks.This step is followed by an optional step of using inkjet printer toprint all cell areas (or areas excluding laser-ablated contacts) withundoped Si (or glass) nano-particle ink. This is followed by sinteringof the ink as required by specific ink handling instructions. Thepurpose of the undoped ink is to use it to randomly texture the oxidesurface which improves the Lambertian properties of the back mirror—thusenhancing efficiency. FIG. 3( f) illustrates the inkjet-printed (andoptional sintered) base and emitter dopants and the inkjet-printedundoped silicon nano-particles that form a blanket textured surfacelayer.

As shown in FIG. 2, the next step is to anneal the inkjet-printed boron,phosphorous, and undoped ink to form n⁺⁺ and P⁺⁺ emitter contactregions. In addition, the annealing step may either be followed by or beintegrated with another anneal in a low O₂ environment which serves tooxidize the undoped silicon particles and create a randomly texturedoxide surface. FIG. 3( g) illustrates the selectively doped base andemitter regions as well as the surface-textured silicon oxide layer.

As shown in FIG. 2, the next step is metallization. First, the backsideof the substrate is cleaned to remove the dopant residue (phosphorousand boron glass) in a diluted HF solution. The LPCVD nitride serves asan etching stop to the dopant residue etching. Next, the contact areasare cleaned for good metal adhesion and electrical contacts. A mildselective silicon etch may be used to clean the area. Although there areseveral ways to perform metallization, a specific implementation with afew variations is described for explanatory purposes. As an example, ametal stack of nickel/copper/nickel (Ni/Cu/Ni) with Cu thickness in therange of 10 to 50 μm can be electroless plated. The thin Ni layer underthe Cu serves as a Cu barrier to prevent Cu diffusion into silicon,while the Ni layer on top of the Cu layer serves as a passivation layerto prevent Cu surface oxidation and corrosion. In general the platingscheme may be electroplating, electroless or emulsions, or any othermetal plating technique (the preferred scheme is electroless and themetal of choice is a Ni+Cu+Ni stack). However, it is not limited to thisstack either for barrier (Ni) or for the main (Cu) metal. Anotherpossibility is an Ni/Ag stack. FIG. 3( h) illustrates thecross-sectional schematic view of the fabricated solar cell after itsbackside metallization steps.

As shown in FIG. 2, the last step of the cell making process is applyinga reinforcement plate on the backside of the solar cell. This step isnecessary if the solar cell silicon substrate is thin, such as thinnerthan 150 μ. The material of the reinforcement plate is preferred to be aPV-grade material, such as PTFE. The PTFE plate/sheet may bepre-laminated through an adhesive layer, such as PV-grade EVA, Z68 orsilicone. Before laminating the PTFE plate on to the solar cell,through-holes or openings have to be made so that the electrical metalcontacts may be accessed from the backside. The opening or through-holeformation may be achieved by mechanical punching/stamping or by lasercutting. In the last step, as shown in FIG. 3( i), the patterned PTFEwith adhesive layer is laminated on the backside of the solar cell withproper alignment.

FIGS. 4( a-b) illustrate backside views of two types of backsidereinforcement plates with through plate openings or grid-shaped ribstructures. As shown in FIG. 4( a), the PTFE reinforcement plate hasregular through-hole openings for backside solar cell metal contactaccess. The thickness of the PTFE plate is preferably in the range of0.1 mm to 0.5 mm. The through-hole diameter is preferably in the rangeof 1 mm to 5 mm and the pitch of the holes is preferably in the range of5 mm to 50 mm—depending on the metal finger pattern and metal fingerthickness on the back of the solar cell. As shown in FIG. 4( b), thegrid-shaped backside reinforcement may also provide mechanical supportfor the thin solar wafer. The width of the grid line may be in the rangeof 0.3 mm to 1 mm, and the thickness of the grid line can be in therange of 50 μm to 300 μm. The opening shape may be square, rectangular,circular, or other shapes providing access to the cell backside. In thecase of square shape openings as shown, the size of the squares may bein the range of 5 mm×5 mm to 50 mm×50 mm

FIGS. 5( a-b) illustrate two metal busbar designs. An importantattribute of a thin, yet high efficiency cell design is the busbardesign. The standard busbar design is a dual bus bar design withinter-digitated metal pattern, shown in FIG. 5( a). A consideration ofis that it requires thick metal in the back because the current has tobe carried by the fingers all the way from one edge of the substrate tothe other. The line presents a large resistive loss of power. A thickermetal typically in the >30 μm range will work for standard a siliconcell ˜150 μm thick. However, thin silicon substrate (<150 μm) backcontacted solar cells may not be able to withstand the stresses of >30μm Cu metal lines. Hence, there is a need for alternatives in the busbardesign to enable a very high efficiency, thin, back contacted cell.

FIG. 5( b) illustrates a distributed busbar design. Here, there are Nbus bars for emitter and the same number for the base areas (FIG. 3 isan N=3 design). An advantage of this design is that the thinner fingersare responsible for carrying the current for a much shorter distance,hence dramatically mitigating the resistive losses. All the emitterbusbars are connected together and the base busbars are connectedtogether. Compared to the standard N=1 (dual busbar) for N pairs ofbusbars, the busbar current is reduced by a factor of N. This allows Cuthickness to be reduced by a factor of N without compromising theresistive losses, enabling Cu thickness between 5-10 μm for N=3-4. Forthin silicon cells this is a major advantage. A potential considerationwith the distributed bus bars is increased contact recombination andelectrical shading because of a larger metal contact area. However, thismay be mitigated by making a slotted busbar design in which the contactto underlying silicon is in slots, but the overhanging metal joinstogether to form a continuous line—this requires that the spacingbetween the slots is no more than twice the thickness of the metal. Notethat the busbar design may be decoupled from the process flow discussedabove as it only dictates the pattern in which the laser ablates thedielectric and the thin metal layer.

FIG. 6 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer—referred to hereinafter as aFlow-1.2 cell. The back junction/back contact solar cell has lightlydoped epitaxial emitter everywhere except under contacts (where it isdoped heavily to form the selective emitter contacts), front side andbackside PECVD silicon nitride and thermal oxide thin layers forpassivation and anti-reflection coating (ARC), optional backside PECVDaluminum oxide (replacing oxide/PECVD SiN on the backside), laserablated contact openings, inkjet printed dopants, electroless-platedmetallization, and substrate reinforcement. The substrate reinforcementplate is shown, as an example, to be attached with alignment to thebackside of the cell. A difference between the Flow-1.2 cell andFlow-1.1 cell is that Flow-1.2 cell uses two separated PECVD siliconnitride (or backside aluminum oxide) depositions to replace thesingle-step double-sided LPCVD silicon nitride deposition in theFlow-1.1 cell. There are several purposes for the change: (1)Electrically, it provides a built-in electric field by the isolatedfixed charge within the PECVD silicon nitride film for repelling theminority carriers from the potential recombination sites at the siliconsurfaces; (2) PECVD silicon nitride or aluminum oxide deposition isconducted at a much lower temperature, in the range of 300° C. to 400°C., than the LPCVD silicon nitride deposition temperature, in the rangeof 700° C. to 800° C. (lower deposition temperature not only has lessinfluence to the substrate doping profile but also reduced thefabrication costs); (3) The separated frontside and backside PECVDdeposition allows tuning of the front and back passivation layerthickness and properties independently for optimization of electricaland optical performance of the passivation, anti-reflection, and totalinternal reflection effects.

FIG. 7 is a block diagram of a fabrication process flow for making theFlow-1.2 solar cell of FIG. 6. As described, compared to the Flow-1.1cell, a difference in the block diagram for Flow-1.2 cell is the fourthstep, which is PECVD silicon nitride deposition on frontside and PECVDaluminum oxide or PECVD silicon nitride deposition on backside. Theremaining process sequences and steps are identical to the Flow-1.1.

FIG. 8 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-2.1 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) as described earlier, two-sided thermal oxide and LPCVDsilicon nitride thin layers for passivation and anti-reflection coating(ARC), respectively, laser ablated contact openings, inkjet printeddopants, inkjet-deposited metal inks, electroless-plated metallization,and substrate reinforcement. The substrate reinforcement plate is shown,as an example, to be attached with alignment to the backside of thecell. A difference between the Flow-2.1 cell and the described Flow 1.1cell is that there is a metal inkjet printing and sintering step priorto the electroless plating metallization process. Metal inks, such asaluminum (Al) and silver (Ag) nano particle inks, are selectivelydeposited on top of both the base and the emitter contact areas. The Inkis deposited such that it follows the shape of the emitter and the basefingers and busbars. After the inkjet printing, the printed Al ink issintered at elevated temperature, in the range of 500° C. to 575° C.,that would also sinter the Ag ink. An advantage of the added inkjetprinting and sintering step is to provide better electrical contact tothe silicon.

FIG. 9 is a block diagram of fabrication process flow of making theFlow-2.1 solar cell. Compared to the Flow-1.1 cell, a difference in theblock diagram for Flow-2.1 cell is the added step prior to electrolessplating. The added step is inkjet printing AL/Ag or Ni nanoparticle inkon busbars and interdigitated fingers with optional thermalannealing/sintering. The rest process sequences and steps are identicalto the Flow-1.1 cell as described.

FIG. 10 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-2.2 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) as described earlier, front side and backside PECVDsilicon nitride and thermal oxide thin layers for passivation andanti-reflection coating (ARC), optional backside PECVD aluminum oxide,laser ablated contact openings, inkjet printed dopants, inkjet-depositedmetal inks, electroless-plated metallization, and substratereinforcement. The substrate reinforcement plate is shown, as anexample, to be attached with alignment to the backside of the cell. Adifference between the Flow-2.2 cell and Flow-2.1 cell is that Flow-2.2cell use two separated PECVD silicon nitride (or backside aluminumoxide) depositions to replace the single-step double-sided LPCVD siliconnitride deposition in the Flow-2.1 cell.

FIG. 11 is a block diagram of the fabrication process flow for makingthe Flow-2.2 solar cell. As described, compared to the Flow-2.1 cell, adifference in the block diagram for Flow-2.2 cell is the fourth step,which is PECVD silicon nitride deposition on frontside and PECVDaluminum oxide or silicon nitride deposition on backside. The restprocess sequences and steps are identical to the Flow-2.1 cell asdescribed.

FIG. 12 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-3.1 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) (the steps leading to the formation of selective emitterare described previously), two-sided thermal oxide and LPCVD siliconnitride thin layers for passivation and anti-reflection coating (ARC),respectively, laser ablated contact openings, spray coated dopants,electroless-plated metallization, and substrate reinforcement. Thesubstrate reinforcement plate is shown, as an example, to be attachedwith alignment to the backside of the cell. The final structure of theFlow-3.1 cell is identical to the Flow-1.1 as shown in FIG. 1. Howeverthe fabrication process is slightly different for the dopant depositionmethods and the contact opening sequence. Specifically, the phosphorousand boron liquid dopants are spray coated in two separated steps andcontact openings of each polarity are formed just prior to the separatedliquid dopant coating step.

FIG. 13 is a block diagram of the fabrication process flow for makingthe Flow-3.1 solar cell. FIGS. 14( a-k) are cross-sectional schematicviews of the Flow-3.1 solar cell after key fabrication process steps.The steps shown—including surface texturing, thin epitaxial emitterlayer growth, thermal oxidation, and LPCVD silicon nitride depositionsteps—are the same for the Flow-1.1 cell described and illustrated inFIG. 2 and FIGS. 3( a-d). In the next step, as shown in FIG. 14( e),only the base contacts are opened by pulsed laser ablation. Phosphorousliquid dopant is then spray coated—FIG. 14( f) shows the curedphosphorous dopant layer. Next, the emitter contacts are opened bypulsed laser ablation of the dielectric layer stacks on top of thesilicon surface, as shown in FIG. 14( g). Then the emitter (boron)dopant liquid is spray coated and cured, as shown in FIG. 14( h). Therest of cell processing steps from FIGS. 14( i) to 14(k) are the same asdescribed for Flow-1.1 cell.

FIG. 15 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-3.2 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) (the steps leading to the formation of selective emitterare describes previously), front side and backside PECVD silicon nitrideand thermal oxide thin layers for passivation and anti-reflectioncoating (ARC), optional backside PECVD aluminum oxide replacingoxide/silicon nitride sandwich, laser ablated contact openings,spray-coated dopants, electroless-plated metallization, and substratereinforcement. The substrate reinforcement plate is shown, as anexample, attached with alignment to the backside of the cell. Adifference between the Flow-3.2 cell and Flow-3.1 cell is that Flow-3.2cell uses two separated PECVD silicon nitride (or backside aluminumoxide) depositions to replace the single-step double-sided LPCVD siliconnitride deposition in the Flow-3.1 cell.

FIG. 16 is a block diagram of fabrication process flow of making theFlow-3.2 solar cell. As described, compared to the Flow-3.1 cell, adifference in the block diagram for Flow-3.2 cell is the fourth step,which is PECVD silicon nitride deposition on front side and PECVDaluminum oxide or PECVD silicon nitride deposition on backside. The restprocess sequences and steps are identical to the Flow-3.1 cell asdescribed.

FIG. 17 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-4.1 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) (where the steps leading to the formation of selectiveemitter are described previously), two-sided thermal oxide and LPCVDsilicon nitride thin layers for passivation and anti-reflection coating(ARC),respectively, laser ablated contact openings, spray coateddopants, inkjet-deposited metal inks, electroless-plated metallization,and substrate reinforcement. The substrate reinforcement plate is shown,as an example, attached with alignment to the backside of the cell. Adifference between the Flow-4.1 cell and the described Flow 3.1 cell isthat there is a metal inkjet printing and sintering step prior to theelectroless plating metallization process. Metal inks, such as aluminum(Al) and silver (Ag) nano particle ink, are selectively deposited on topof both the base and the emitter contact areas. The inks are depositedsuch that they follow the shape of the emitter and the base fingers andbusbars. After the inkjet printing, the printed inks are sintered atelevated temperature, in the range of 500° C. to 575° C., in the case ofaluminum ink which would also sinter the Ag ink.

FIG. 18 is a block diagram of fabrication process flow of making theFlow-4.1 solar cell. Compared to the Flow-3.1 cell, a difference in theblock diagram for Flow-4.1 cell is the added step prior to electrolessplating. The added step is inkjet printing Al/Ag or Ni nanoparticle inkon busbars and interdigitated fingers with optional thermalannealing/sintering. The rest process sequences and steps are identicalto the Flow-3.1 cell as described.

FIG. 19 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-4.2 cell. The back contact solar cell has epitaxial selectiveemitter (ESE) (where the steps leading to the formation of selectiveemitter are described previously), front side and backside PECVD siliconnitride and thermal oxide thin layers for passivation andanti-reflection coating (ARC), optional backside PECVD aluminum oxide,laser ablated contact openings, spray coated dopants, inkjet-depositedmetal inks, electroless-plated metallization, and substratereinforcement. The substrate reinforcement plate is shown, as anexample, attached with alignment to the backside of the cell. Adifference between the Flow-4.2 cell and Flow-4.1 cell is that Flow-4.2cell uses two separated PECVD silicon nitride (or backside aluminumoxide) depositions to replace the single-step double-sided LPCVD siliconnitride deposition in the Flow-4.1 cell.

FIG. 20 is a block diagram of fabrication process flow of making theFlow-4.2 solar cell. As described, compared to the Flow-4.1 cell, adifference in the block diagram for Flow-4.2 cell is the fourth stepwhich is PECVD silicon nitride deposition on front side and PECVDaluminum oxide or silicon nitride deposition on backside. The restprocess sequences and steps are identical to the Flow-4.1 cell asdescribed.

The above described cell process variations have common epitaxialemitter layers. Alternatively, the emitter layer may be formed by adopant diffusion process such as furnace annealing using boroncontaining precursors or the deposition of boron silicate glass (BSG) onthe wafer surface followed by annealing. All eight flows along withtheir variations discussed for the epitaxial emitter in theaforementioned section are equally applicable here. The difference isthat the epitaxial emitter step is substituted by the furnace annealingin boron containing gases or BSG deposition and annealing steps. Thissubstitution is demonstrated for only one process (two sided LPCVD SiN,with inkjet dopants, with no metal inkjet) in FIGS. 21-23. However, itis equally applicable to all other seven embodiments. The epitaxialemitter deposition step is replaced by three steps of BSG deposition onthe emitter side, furnace annealing to form p⁺ selective emitter on thebackside, and BSG strip and clean.

FIG. 21 is a cross-sectional schematic view of a back contact solar cellthat is made of a bulk silicon wafer. The solar cell is referred to as aFlow-5.1 cell. The back contact solar cell has a dopant-diffusion formedemitter layer, two-sided thermal oxide and LPCVD silicon nitride thinlayers for passivation and anti-reflection coating (ARC), respectively,laser ablated contact openings, inkjet printed dopants,electroless-plated metallization, and substrate reinforcement.

FIG. 22 is a block diagram of the fabrication process flow for makingthe Flow-5.1 solar cell. FIGS. 23( a-k) are cross-sectional schematicviews of the Flow-5.1 solar cell after key fabrication process steps.The first surface texturing step is same as describe for Flow 1.1 cell.As shown in FIG. 23( b), a thin layer of BSG is deposited on thesubstrate backside—preferably by the atmospheric pressure chemical vapordeposition (APCVD) process. Next, a furnace annealing process isconducted that forms the diffused p⁺ emitter layer on the backside, asshown in FIG. 23( c). FIG. 23( d) shows the removal of the remaining BSGlayer followed by wafer cleaning The removal of the remaining BSG layermay be done by diluted HF solution etching and the substrate cleaningmay be done by standard SC1 and SC2 etching. The rest of process stepsas shown from FIG. 23( e) to FIG. 23( k) are same as described for theFlow-1.1 cell accordingly.

In operation, the disclosed subject matter provides both the structuresand methods for manufacturing novel high-efficiency back junction/backcontacted solar cells—preferably on thin crystalline semiconductorwafers (preferably monocrystalline silicon). More specifically, thesesolar cell wafers may be produced by techniques including slicing andcleaving thin crystalline substrates from thicker wafers or ingot piecesusing techniques such as proton implantation and stress-inducedcleaving/slicing. Generally, the particular concept of manufacturingmethods as it pertains to all aspects of processing very thin solar cellwafers can be extended to other types of materials and to wafer-basedapproach. Key attributes of the detailed solar cell include reducedmanufacturing cost per watt and relatively high conversion efficiencies,and thus performance. Specifically, this stems from the unique design,which entails manufacturing back junction/back contacted solar cells,yielding very high performance on very thin mono/multi-crystallinesemiconductor wafers, yielding very low manufacturing cost. While theembodiments disclosed are described utilizing monocrystalline siliconwafers, these embodiments are also applicable to other elemental andcompound semiconductor materials such as GaAs (gallium arsenide), aswell as heterojunctions and multijunction solar cells utilizing siliconor other semiconductor materials.

Further, the disclosure provides designs and methods of manufacturingback contact/junction solar cell using planar silicon substrates. Otherdisclosed aspects include the use of sub-nanosecond pulsed laserprocessing (from femtosecond to hundreds of picoseconds) to support thefabrication of back junction back contact solar cells.

In one embodiment, the back contact solar cell has epitaxial selectiveemitter (ESE), two-sided thermal oxide and LPCVD silicon nitride thinlayers for passivation and anti-reflection coating (ARC), laser ablatedcontact openings, inkjet printed dopants, electroless-platedmetallization, and substrate reinforcement. The substrate reinforcementplate is shown, as an example, attached with alignment to the backsideof the cell. The backside reinforcement plate may be a continuous platewith through-holes for accessing the emitter and base metal contacts onthe backside of the solar cell. Alternatively, the backsidereinforcement plate may have more or larger openings that are assembledto a grid-shaped structure for lighter and easier substrate backsideaccess at solar cell module level.

In another embodiment, the double-sided LPCVD silicon nitridepassivation layer is replaced by two separated front side and backsidePECVD silicon nitride depositions. In another embodiment, the backsidePECVD silicon nitride layer is replaced by a thin aluminum oxide layer.

In another embodiment, there is an inkjet printing of metal nanoparticleink and its sintering process prior to the electroless metal platingprocess. Also disclosed is aerosol printed Al ink.

In one embodiment the inkjet dopant ink used is comprised of siliconnano-particles with p and n-type dopants. In another embodiment, theinkjet liquid dopant printing process is replaced by a dopant liquidspray coating process.

In another embodiment, the forming of the backside epitaxial emitterlayer is replaced by forming the emitter layer by a dopant diffusionprocess. This includes, but is not limited to Atmospheric pressureChemical vapor Deposition (APCVD) processes.

The foregoing description of the preferred embodiments is provided toenable any person skilled in the art to make or use the claimed subjectmatter. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without the use of theinnovative faculty. Thus, the claimed subject matter is not intended tobe limited to the embodiments shown herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

What is claimed is:
 1. A back contact back junction thin solar cell,comprising: a semiconductor wafer with a thickness in the range of 50 to250 microns, comprising: a doped base region, a light capturingfrontside surface, and a doped backside emitter region with a dopingpolarity opposite said doped base region; a frontside dielectric layeron said frontside surface and a backside dielectric layer on saidbackside emitter region; a frontside passivation layer on said frontsidedielectric layer; a backside passivation layer on said backsidedielectric layer; wherein said backside passivation dielectric layer andsaid backside dielectric layer form a mirror; and backside emittercontacts and backside base contacts connected to emitter regions andbase regions through laser ablated contact openings in said backsidepassivation layer and said backside dielectric layer, said backsideemitter contacts and backside base contacts connected to metalinterconnects forming a metallization pattern of interdigitated fingersand busbars on the backside of said back contact back junction thinsolar cell.
 2. The back contact back junction thin solar cell of claim1, wherein said doped backside emitter region is an epitaxial emitterregion.
 3. The back contact back junction thin solar cell of claim 1,wherein said doped backside emitter region is an epitaxial in-situ dopedemitter region.
 4. The back contact back junction thin solar cell ofclaim 1, wherein said frontside dielectric layer and said backsidedielectric layer are thermal oxide layers.
 5. The back contact backjunction thin solar cell of claim 1, further comprising a permanentbackside grid-shaped support reinforcement.
 6. The back contact backjunction thin solar cell of claim 1, wherein said metallization patternof interdigitated fingers and busbars is a distributed busbar array. 7.The back contact back junction thin solar cell of claim 1, wherein thepassivation layers comprise a thin silicon nitride layer.
 8. The backcontact back junction thin solar cell of claim 1, wherein thepassivation layers comprise a thin aluminum oxide layer.
 9. A method forthe manufacture of a back contact back junction thin solar cell from adoped crystalline semiconductor wafer, said wafer comprising a frontsideand backside, the method comprising: texturing said wafer frontside;depositing an epitaxial emitter region on said wafer backside;depositing a surface passivation layer on said wafer frontside and saidwafer backside; forming interdigitated emitter and base contact openingsin said wafer backside surface passivation layer by laser ablation ofthe wafer backside surface passivation layer with a pulsed picosecondlaser; doping the interdigitated pattern of said emitter and basecontact openings to form emitter regions and base regions; andmetalizing the cell backside to form backside base and emitter contactsin the pattern of interdigitated fingers and busbars.
 10. The method ofclaim 9, wherein said epitaxial emitter region is in-situ doped with athickness in the range of 0.5 to 5 microns.
 11. The method of claim 9,wherein said surface passivation layer comprises a thermally grown oxidelayer and a silicon nitride layer.
 12. The method of claim 9, whereinsaid surface passivation layer comprises a thermally grown oxide layerand an LPCVD silicon nitride layer.
 13. The method of claim 9, whereinsaid surface passivation layer comprises a thermally grown oxide layerand a PECVD silicon nitride layer.
 14. The method of claim 9, whereinsaid surface passivation layer comprises a thermally grown oxide layerand an aluminum oxide layer.
 15. The method of claim 9, wherein saidstep of doping the interdigitated pattern of said emitter and basecontact openings to form emitter regions and base regions uses an inkjetprinter to print silicon nano-particle inks on said interdigitatedpattern of said emitter and base contact openings.
 16. The method ofclaim 9, further comprising the step of printing said wafer frontsideand backside with an undoped silicon nano-particle ink using an inkjetprinter and sintering of said ink to texture said wafer frontside andbackside.
 17. The method of claim 9, wherein said metallization contactscomprise layers of nickel and silver.
 18. The method of claim 9, whereinsaid metallization contacts comprise layers formed by aluminum ink. 19.A back contact back junction thin solar cell, comprising: semiconductorwafer with a thickness in the range of 50 to 250 microns, comprising: adoped base region, a light capturing frontside surface, and a dopedbackside emitter region with a doping polarity opposite said doped baseregion; a frontside first dielectric layer on said frontside surface anda backside first dielectric layer on said backside emitter region; afrontside second dielectric layer on said frontside first dielectriclayer, the combination serving as frontside passivation layer; abackside second dielectric layer on said first backside dielectriclayer, the combination serving as backside passivation layer; whereinsaid backside first and second dielectric layers form a dielectricmirror; backside emitter contacts and backside base contacts connectedto emitter regions and base regions through contact openings in saidbackside first and second dielectric layers, said backside emittercontacts and backside base contacts connected to metal interconnectsforming a metallization pattern of interdigitated fingers and busbars onthe backside of said back contact back junction thin solar cell; and atleast one permanent support reinforcement positioned on the frontside orbackside of said back contact back junction thin solar cell.
 20. Theback contact back junction solar cell of claim 19, wherein said contactopenings are formed by pulsed laser ablation.
 21. The back contact backjunction solar cell of claim 19, wherein said contact openings areformed by sub-nanosecond-pulse duration pulsed-laser ablation.